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description the pbl 386 14/1 subscriber line interface circuit (slic) is a 90 v bipolar integrated circuit for use in isdn network terminal adapters and other short loop telecommunication equipment which often are remote powered, and by that, the available power is limited. the pbl 386 14/1 has been optimized for low total line interface cost, low power and requires a minimum of external components. the pbl 386 14/1 has constant current feed, programmable to max 30ma. the slic uses a first battery voltage for on-hook . a second battery voltage is used for off-hook and must be connected, to reduce short loop power dissipation. the slic automatically switches between the two battery supply voltages without need for external components or external control. the loop current controls the switching between on-hook and off-hook battery. the slic incorporates loop current, ground key and ring trip detection functions. the pbl 386 14/1 is compatible with loop start signalling. two- to four-wire and four- to two-wire voice frequency (vf) signal conversion is accomplished by the slic in conjunction with either a conventional codec/filter or with a programmable codec/filter, e.g. slac, sicofi, combo ii. the programmable line terminating impedance could be complex or real to fit every market. longitudinal voltages are suppressed by a feedback loop in the slic and the longitudinal balance specifica- tions meet bellcore tr909 requirements. the pbl 386 14/1 package is a very pcb space efficient 28-pin ssop. figure 1. block diagram. february 2000 pbl 386 14/1 subscriber line interface circuit applications ? isdn network terminals ? shortloop applications key features ? small footprint with ssop package ? on-hook and off-hook battery with automatic switching, controlled by loop current ? on-hook battery current is limited to 6 ma ? 37 mw on-hook power dissipation in active state ? metering 0.5 vrms (0.7 vpeak) ? adaptive overhead voltage the overhead voltage follows 1vpeak pbl 386 14/1 2 maximum ratings parameter symbol min max unit temperature, humidity storage temperature range t stg -55 +150 c operating temperature range t amb -40 +110 c operating junction temperature range, note 1 t j -40 +140 c power supply, 0 c t amb +70 c v cc with respect to agnd v cc -0.4 6.5 v v ee with respect to agnd v ee v bat 0.4 v v bat2 with respect to a/bgnd v bat2 v bat 0.4 v v bat with respect to bgnd, continuous v bat -75 0.4 v v bat2 with respect to bgnd, 10 ms v bat2 -80 0.4 v power dissipation continuous power dissipation at t amb +70 cp d 0.8 w ground voltage between agnd and bgnd v g -5 vcc v relay driver ring relay supply voltage bgnd +13 v ring relay current 75 ma ring trip comparator input voltage v dt , v dr v bat v cc v input current i dt , i dr -5 5 ma digital inputs, outputs (c1, c2, c3, det) input voltage v id -0.4 v cc v output voltage (det not active) v od -0.4 v cc v output current (det) i od 30 ma tipx and ringx terminals, 0 c < t amb < +70 c, v bat = -50 v tipx or ringx current i tipx , i ringx -110 +110 ma tipx or ringx voltage, continuous (referenced to agnd), note 2 v ta , v ra v bat 2v tipx or ringx, pulse < 10 ms, t rep > 10 s, note 2 v ta , v ra v bat - 20 5 v tipx or ringx, pulse < 1 m s, t rep > 10 s, note 2 v ta , v ra v bat - 40 10 v tip or ring, pulse < 250 ns, t rep > 10 s, note 3 v ta , v ra v bat - 70 15 v recommended operating condition parameter symbol min max unit ambient temperature t amb 0 +70 c v cc with respect to agnd v cc 4.75 5.25 v v ee with respect to agnd v ee v bat -4.75 v v bat with respect to bgnd v bat -58 -10 v v bat2 with respect to bgnd v bat2 v bat -10 v notes 1. the circuit includes thermal protection. operation above max. junction temperature may degrade device reliability. 2. a diode in series with the vbat input increases the permitted continuous voltage and pulse < 10 ms to -85 v. a pulse 1 m s is increased to the greater of |-70v| and |vbat -40v|. 3. r f1 and r f2 3 20 w is also required. pulse is supplied to tip and ring outside r f1 and r f2 .
pbl 386 14/1 3 electrical characteristics 0 c t amb +70 c, v cc = +5v 5 %, v ee = -5v 5%, v bat = -58v to -40v, v bat2 = -22v, r lc =18.7k w (i l = 27 ma), r l = 600 w , r ld = 50 k w , r f1 , r f2 = 0 w , r ref = 15k w , c hp = 68nf, c lp =0.47 m f, r t = 120 k w , r rx = 120 k w , current definition: current is positive if flowing into a pin. active state includes active normal unless otherwise specified. battery definition: v bat = on-hook battery, v bat2 = off-hook battery. ref parameter fig conditions min typ max unit two-wire port overload level, v tro 2 active state off-hook, i ldc 3 10 ma 1% thd, note 1 1.0 v peak on-hook, i ldc 5 ma 1.0 v peak metering i ldc 3 10 ma z lttx = 200 w , f = 16 khz 0.7 v peak input impedance, z tr note 2 z t /200 longitudinal impedance, z lot , z lor 0 < f < 100 hz 20 35 w /wire longitudinal current limit, i lot , i lor active state 12 ma rms /wire longitudinal to metallic balance, b lm ieee standard 455-1985, ztrx = 736 w 0.2 khz < f < 1.0 khz 53 70 db 1.0 khz < f < 3.4 khz 53 70 db longitudinal to metallic balance, b lme 3 active state e lo b lme = 20 ? log 0.2 khz f 1.0 khz 53 70 db v tr 1.0 khz < f < 3.4 khz 53 70 db longitudinal to four-wire balance, b lfe 3 active state e lo b lfe = 20 ? log 0.2 khz f 1.0 khz 59 70 db v tx 1.0 khz < f < 3.4 khz 59 70 db metallic to longitudinal balance, b mle 4 active state v tr b mle = 20 ? log ;e rx = 0 0.2 khz < f < 3.4 khz 40 58 db v lo figure 2. overload level, v tro , two-wire port 1 << r l , r l = 600 w wc r t = 120 k w , r rx = 120 k w figure 3. longitudinal to metallic (b lme ) and longitudinal to four-wire (b lfe ) balance 1 << 150 w , r lr = r lt = r l /2= 300 w wc r t = 120 k w , r rx = 120 k w pbl 386 14/1 tipx ringx rsn vtx r t r rx e rx r l v tro i ldc c pbl 386 14/1 tipx ringx rsn vtx r t r rx v tx r lt c v tr r lr e lo
pbl 386 14/1 4 parameter fig conditions min typ max unit four-wire to longitudinal balance, b fle 4 active state e rx b fle = 20 ? log v lo 0.2 khz < f < 3.4 khz 40 58 db two-wire return loss, r |z tr + z l | r = 20 ? log |z tr - z l | 0.2 khz < f < 0.5 khz 25 db 0.5 khz < f < 1.0 khz 27 db 1.0 khz < f < 3.4 khz, note 3 23 db tipx idle voltage, v ti active normal, i l = 0 - 1.3 v ringx idle voltage, v ri active normal, i l = 0 v bat +3.1 v |v tr | active, i l = 0 |v bat +5.5| |v bat + 4.5| v four-wire transmit port (v tx ) overload level, v txo 5 off-hook, i l 3 10ma load impedance > 20 k w , 0.5 v peak on-hook, i l 5ma 1% thd, note 4 0.5 v peak output offset voltage, d v tx -60 60 mv output impedance, z tx 0.2 khz < f < 3.4 khz 5 20 w four-wire receive port (rsn) receive summing node (rsn) dc voltage i rsn = 0 ma gnd +25 mv receive summing node (rsn) impedance 0.2 khz < f < 3.4 khz 10 50 w receive summing node (rsn) 0.3 khz < f < 3.4 khz current (i rsn ) to metallic loop current (i l ) 400 ratio gain, a rsn frequency response two-wire to four-wire, g 2-4 6 relative to 0 dbm, 1.0 khz. e rx = 0 v 0.3 khz < f < 3.4 khz -0.15 0.15 db f = 8.0 khz, 12 khz, 16 khz -0.5 0 0.1 db figure 4. metallic to longitudinal and four-wire to longitudinal balance 1 << 150 w , r lt = r lr = r l /2 =300 w w c r t = 120 k w , r rx = 120 k w figure 5. overload level, v txo , four-wire transmit port 1 << r l , r l = 600 w w c r t = 120 k w , r rx = 120 k w ref pbl 386 14/1 tipx ringx rsn vtx r t r rx e rx r lt c v tr r lr v lo pbl 386 14/1 tipx ringx rsn vtx r t r rx r l i ldc c e l v txo
pbl 386 14/1 5 four-wire to two-wire, g 4-2 6 relative to 0 dbm, 1.0 khz. e l = 0 v 0.3 khz < f < 3.4 khz -0.15 0.15 db f = 8 khz, 12 khz, -1.0 -0.2 0 db 16 khz -1.0 -0.3 0 db four-wire to four-wire, g 4-4 6 relative to 0 dbm, 1.0 khz. e l = 0 v 0.3 khz < f < 3.4 khz -0.15 0.15 db insertion loss two-wire to four-wire, g 2-4 6 0 dbm, 1.0 khz, note 5 v tx g 2-4 = 20 ? log ,e rx = 0 v tr -6.22 -6.02 -5.82 db four-wire to two-wire, g 4-2 6 0 dbm, 1.0 khz, notes 5, 6 v tr g 4-2 = 20 ? log ,e g = 0 e rx -0.2 0.2 db gain tracking two-wire to four-wire r ldc 2k w 6 ref. -10 dbm, 1.0 khz, note 7 -40 dbm to +3 dbm -0.1 0.1 db -55 dbm to -40 dbm -0.2 0.2 db four-wire to two-wire r ldc 2k w 6 ref. -10 dbm, 1.0 khz, note 7 -40 dbm to +3 dbm -0.1 0.1 db -55 dbm to -40 dbm -0.2 0.2 db noise idle channel noise at two-wire c-message weighting 7 12 dbrnc (tipx-ringx) psophometrical weighting -83 -78 dbmp note 8 harmonic distortion two-wire to four-wire 6 0 dbm, 1.0 khz test signal -50 db four-wire to two-wire 0.3 khz < f < 3.4 khz -50 db battery feed characteristics constant loop current, i lconst 13 i lprog = 500 r lc 18 < i lprog < 30 ma 0.95 i lprog i lprog 1.05 i lprog ma ref parameter fig conditions min typ max unit figure 6. frequency response, insertion loss, gain tracking. 1 << r l , r l = 600 w w c r t = 120 k w , r rx = 120 k w pbl 386 14/1 tipx ringx rsn vtx r t r rx e rx r l v tr i ldc c e l v tx
pbl 386 14/1 6 loop current detector programmable threshold, i det i lth = 500 0.9?i lth i lth 1.1?i lth ma i lth > 10 ma r ld ground key detector ground key detector threshold i ltipx and i lringx current difference to trigger ground key det. 11 15 19 ma ring trip comparator offset voltage, d v dtdr source resistance, r s = 0 w -20 0 20 mv input bias current, i b i b = (i dt + i dr )/2 -50 -20 na input common mode range, v dt , v dr v bat +1 -1 v ring relay driver saturation voltage, v ol i ol = 50 ma 0.2 0.5 v off state leakage current, i lk v oh = 12 v 100 m a digital inputs (c1, c2, c3) input low voltage, v il 0 0.5 v input high voltage, v ih 2.5 v cc v input low current, |i il |v il = 0.5 200 m a input high current, i ih v ih = 2.5 v 200 m a detector output (det) output low voltage, v ol i ol = 1 ma 0.1 0.6 v internal pull-up resistor to v cc 10 k w power dissipation (v bat = -48v, v bat2 = -22v, note 9) p 1 open circuit state 15 18 mw p 2 @ vee=-5v active state i lo = 0 ma, i l = 0 ma 37 44 mw p 3 @ vee=vb2 active state i lo = 0 ma, i l = 0 ma 40 47 mw p 4 @ vee = -5v active r l = 300 w (off-hook) 415 mw p 5 @ vee = -5v active r l = 600 w (off-hook) 200 mw power supply currents (v bat = -48v) v cc current, i cc open circuit state 1.3 ma v ee current, i ee open circuit state -0.2 -0.1 ma v bat current, i bat open circuit state -0.2 -0.1 ma v cc current, i cc active state i lo = 0 ma, i l = 0 ma 2.1 3.5 ma v ee current, i ee active state i lo = 0 ma, i l = 0 ma 0.1 0.3 ma v bat current, i bat , on-hook active state i lo = 0 ma, i l = 0 ma -0.8 -0.5 ma power supply rejection ratios v cc to 2- or 4-wire port active state, f = 1 khz, v n = 100mv 30 45 db v ee to 2- or 4-wire port active state, f = 1 khz, v n = 100mv 28.5 55 db v bat to 2- or 4-wire port active state, f = 1 khz, v n = 100mv 45 60 db v bat2 to 2- or 4-wire port active state, f = 1 khz, v n = 100mv 28.5 60 db temperature guard junction threshold temperature, t jg 140 c thermal resistance 28-pin ssop, q jp28ssop 55 c/w parameter fig conditions min typ max unit ref
pbl 386 14/1 7 notes 1. the overload level is automatically expanded to 2.5 v peak when the signal level > 1.0 v peak and is specified at the two-wire port with the signal source at the four-wire receive port. 2. the two-wire impedance is programmable by selection of external component values according to: z tr = z t /|g 2-4s a rsn | where: z tr = impedance between the tipx and ringx terminals z t = programming network between the vtx and rsn terminals g 2-4s = transmit gain, nominally = -0.5 a rsn = receive current gain, nominally = 400 (current defined as positive flowing into the receivesumm- ing node, rsn, and when flowing from tip to ring). 3. higher return loss values can be achieved by adding a reactive component to r t , the two-wire terminating impedance programming resistance, e.g. by dividing r t into two equal halves and connecting a capacitor from the common point to ground. 4. the overload level is automatically expanded as needed up to 1.25 v peak when the signal level >0.5 v peak and is specified at the four-wire transmit port, vtx, with the signal source at the two-wire port. note that the gain from the two-wire port to the four-wire transmit port is g 2-4s = -0.5. 5. secondary protection resistors r f impact the insertion loss. the specified insertion loss is for r f = 0. 6. the specified insertion loss tolerance does not include errors caused by external components. 7. the level is specified at the four-wire receive port and referenced to a 600 w programmed two-wire impedance level. 8. the two-wire idle noise is specified with the four-wire receive port grounded (e rx = 0; see figure 6). the four-wire idle noise at vtx is the two-wire value -6 db and is specified with the two-wire port terminated in 600 w (r l ). the noise specification is referenced to a 600 w programmed two-wire impedance level at vtx. the four- wire receive port is grounded (e rx = 0). 9. the v bat2 voltage is optimized for r l =600 w with a programmed linecurrent, i l =27 ma. this gives v bat2 =22 v at the terminal (e.g. calculated to 21.9v).
pbl 386 14/1 8 pin description refer to figure 7. ssop symbol description 1 rrly r ing r e l a y driver output. 2 ts t ip s ense should be connected to tipx. 3 hp h igh p ass connection for ac/dc separation capacitor c hp . other end of c hp connects to ringx (pin 26). 4 ringx the tipx and ringx pins connect to the tip and ring leads of the two-wire interface via overvoltage protection components and ring relay (and optional test relay). 5 bgnd b attery g rou nd , should be tied together with agnd. 6 tipx the tipx and ringx pins connect to the tip and ring leads of the two-wire interface via overvoltage protection components and ring relay (and optional test relay). 7 vbat on-hook battery voltage. negative with respect to bgnd. 8 vbat2 off-hook battery voltage, connected in series with a diode. 9 nc n o c onnect. must be left open. 10 psg p rogrammable s aturation g uard. must be connected to vbat2. 11 lp l ow p ass saturation guard filter capacitor connected here to filter out noise and improve psrr. other end of c lp connects to vbat2. 12 dt input to the ring trip comparator. with dr more positive than dt the detector output, det, is at logic level low, indicating off-hook condition. the ring trip network connects to this input. 13 dr input to the ring trip comparator. with dr more positive than dt the detector output, det, is at logic level low, indicating off-hook condition. the ring trip network connects to this input. 14 nc n o c onnect. must be left open. 15 nc n o c onnect. must be left open. 16 vee -5v power supply, if not -5 v available connect to vb2 or vbat (vb2 lower power dissipation than vbat). 17 ref a 15k w resistor must be connected between this pin and agnd. 18 nc n o c onnect. must be left open. 19 plc p rog. l ine c urrent, the constant current part of the dc feed characteristic is programmed by a resistor connected from this pin to agnd. 20 pld p rogrammable l oop d etector threshold. the loop detection threshold is programmed by a resistor connected from this pin to agnd. 21 vcc +5 v power supply. 22 c3 c1, c2 and c3 are digital inputs c ontrolling the slic operating states. refer to section 23 c2 operating states for details. 24 c1 25 det det ector output. active low when indicating loop or ring trip detection, active high when indicating ground key detection, active low when indicating temperature alarm. 26 rsn r eceive s umming n ode. 400 times the current flowing into this pin equals the metallic (transversal) current flowing from tipx to ringx. programming networks for two-wire impedance and receive gain connect to the receive summing node. 27 agnd a nalog g rou nd , should be tied together with bgnd. 28 vtx transmit vf output. the ac voltage difference between tipx and ringx, the ac metallic voltage, is reproduced as an unbalanced gnd referenced signal at vtx with a gain of -0.5. the two-wire impedance programming network connects between vtx and rsn. }
pbl 386 14/1 9 slic operating states figure 7. pin configuration 28 pin ssop package, top view. state c3 c2 c1 slic operating state active detector 0 0 0 0 open circuit detector is set high 1 0 0 1 ringing state ring trip detector (active low) 2 0 1 0 active state loop detector (active low) 3 0 1 1 active state line voltage measurament (pulse train) 4 1 0 0 active state temperature guard (active low) 5 1 0 1 active state ground key detector (active high) 6 1 1 0 not applicable 7 1 1 1 not applicable table 1. slic operating states. * pins must be left open. 1 2 3 4 5 6 7 8 9 10 11 28 27 26 25 24 23 22 21 20 19 18 ts rrly hp ringx bgnd tipx vbat psg c2 vtx agnd rsn det c3 vcc plc lp *nc c1 vbat2 pld 12 17 dt ref 28-pin ssop 16 vee 15 nc* 13 dr 14 *nc nc*
pbl 386 14/1 10 figure 9. simplified ac transmission circuit. functional description and applications information transmission pbl 386 14/1 + - + - vtx rsn i l / a tipx ringx + - e l + - tip ring r f r f z tr z t v tx v rx z rx i l i l r hp + - z l v tr g rsn 2-4s general a simplified ac model of the transmission circuits is shown in figure 9. circuit analysis yields: v tr = v tx - i l ? 2r f (1) g 2-4s v tx + v rx = i l (2) z t z rx a rsn v tr = i l ? z l - e l (3) where: v tx is a ground referenced version of the ac metallic voltage between the tipx and ringx terminals. v tr is the ac metallic voltage between tip and ring. e l is the line open circuit ac metallic voltage. i l is the ac metallic current. r f is a fuse resistor. g 2-4s is the slic two-wire to four- wire gain (transmit direction) with a nominal value of -0.5. (phase shift 180 .) z l is the line impedance. z t determines the slic tipx to ringx impedance for signal in the 0 - 20khz frequency range. z rx controls four- to two-wire gain. v rx is the analogue ground referenced receive signal. a rsn is the receive summing node current to metallic loop current gain. the nominal value of a rsn = 400 r hp internal resistor appprox. 180 k w two-wire impedance to calculate z tr , the impedance presented to the two-wire line by the slic including the fuse resistor r f , let v rx = 0. from (1) and (2): z tr = z t - 2r f a rsn ? g 2-4s thus with z tr , g 2-4s , a rsn , and r f known: z t = a rsn ? g 2-4s ? (2r f - |z tr |) two-wire to four-wire gain from (1) and (2) with v rx = 0: g 2-4 = v tx = z t / a rsn v tr z t - 2r f a rsn ? g 2-4s four-wire to two-wire gain from (1), (2) and (3) with e l = 0: g 4-2 = v tr = z t ? z l v rx z rx z t - g 2-4s ? ( z l + 2r f ) a rsn in applications where 2r f - z t /( a rsn ? g 2-4s ) is chosen to be equal to z l , the expression for g 4-2 simplifies to: g 4-2 = - z t ? 1 z rx 2 ? g 2-4s four-wire to four-wire gain from (1), (2) and (3) with e l = 0: g 4-4 = v tx = z t ? g 2-4s ? ( z l + 2r f ) v rx z rx z t - g 2-4s ? ( z l + 2r f ) a rsn
pbl 386 14/1 11 figure 10. hybrid function. v t combination codec/filter r tx z b z rx z t vtx rsn v rx pbl 386 14/1 hybrid function the hybrid function can easily be imple- mented utilizing the uncommitted amplifier in conventional codec/filter combinations. please, refer to figure 10. via impedance z b a current proportional to v rx is injected into the summing node of the combination codec/filter amplifier. as can be seen from the expression for the four-wire to four-wire gain a voltage proportional to v rx is returned to v tx . this voltage is converted by r tx to a current flowing into the same summing node. these currents can be made to cancel by letting: v tx + v rx = 0 (e l = 0) r tx z b the four-wire to four-wire gain, g 4-4 , in- cludes the required phase shift and thus the balance network z b can be calculated from: z b = - r tx ? v rx = v tx z t - g 2-4s ? ( z l + 2r f ) - r tx ? z rx ? a rsn z t g 2-4s ? ( z l + 2r f ) when choosing r tx , make sure the output load of the vtx terminal is (r tx //r t in figure 14) > 20 k w . if calculation of the z b formula above yields a balance network containing an inductor, an alternate method is recom- mended. the pbl 386 14/1 slic may also be used together with programmable codec/ filters. the programmable codec/filter allows for system controller adjustment of hybrid balance to accommodate different line impedances without change of hard- ware. in addition, the transmit and receive gain may be adjusted. please, refer to the programmable codec/filter data sheets for design information. longitudinal impedance a feed back loop counteracts longitudinal voltages at the two-wire port by injecting longitudinal currents in opposing phase. thus longitudinal disturbances will ap- pear as longitudinal currents and the tipx and ringx terminals will experience very small longitudinal voltage excursions, leav- ing metallic voltages well within the slic common mode range. the slic longitudinal impedance per wire, z lot and z lor , appears as typically 20 w to longitudinal disturbances. it should be not- ed that longitudinal currents may exceed the dc loop current without disturbing the vf transmission. capacitors c tc and c rc if rfi filtering is needed, the capacitors designated c tc and c rc in figure 13, con- nected between tipx and ground as well as between ringx and ground, may be mounted. c tc and c rc work as rfi filters in con- junction with suitable series impedances (i.e. resistances, inductances). resistors r f1 and r f2 may be sufficient, but series inductances can be added to form a sec- ond order filter. current-compensated in- ductors are suitable since they suppress common-mode signals with minimum influ- ence on return loss. recommended values for c tc and c rc are below 1 nf. lower values impose smaller degradation on re- turn loss and longitudinal balance, but also attenuate radio frequencies to a smaller extent. the influence on the impedance loop must also be taken into consideration when programming the codec. c tc and c rc contribute to a metallic impedance of 1/( p ? f ? c tc ) = 1/( p ? f ? c rc ), a tipx to ground impedance of 1/(2 ? p ? f ? c tc ) and a ringx to ground impedance of 1/(2 ? p ? f ? c rc ) . ac - dc separation capacitor, c hp the high pass filter capacitor connected between terminals hp and ringx pro- vides the separation of the ac and dc signals. c hp positions the low end frequen- cy response break point of the ac loop in the slic. refer to table 1 for recommended value of c hp . example: a c hp value of 68 nf will position the low end frequency response 3db break point of the ac loop at 13 hz (f 3db ) according to f 3db = 1/(2 ? p ? r hp ? c hp ) where r hp = 180 k w .
pbl 386 14/1 12 figure 11. the aov funktion when the aov-pin is left open. (observe, burst undersampled). 1 v peak 2.50 v 2.50 v 2.50 v high-pass transmit filter when codec/filter with a single 5 v power supply is used, it is necessary to separate the different signal reference voltages be- tween the slic and the codec/filter. in the transmit direction this can be done by connecting a capacitor between the vtx output of the slic and the codec/filter input. this capacitor will also form, togeth- er with r tx and/or the input impedance of the codec/filter, a high-pass rc filter. it is recommended to position the 3 db break point of this filter between 30 and 80 hz to get a fast enough response for the dc steps that may occur with dtmf signaling. capacitor c lp the capacitor c lp , which connects between the terminals lp and vbat2, positions the high end frequency break point of the low pass filter in the dc loop in the slic. c lp together with c hp and z t (see section two- wire impedance) forms the total two wire output impedance of the slic. r feed c lp c hp [ w ] [nf] [nf] 2 ? 25 470 68 table 1. c lp and c hp values. adaptive overhead voltage, aov the adaptive overhead voltage feature minimizes the power dissipation and at the same time provides a flexible solution for different system requirements and possi- ble future changes concerning voice, me- tering and other signal levels. this is done by using an overhead voltage which auto- matically adapts to the signal level (voice + metering). the pbl38615/1 will behave as a slic with fixed overhead for signals in the 0- 20khz range and with an amplitude less than 1v peak . for signal amplitudes between 1v peak and 2.5v peak the adaptive overhead function will expand the overhead voltage making it possible for the signal to propa- gate through the slic without distortion ( this is the total sum of voice and metering signal). the expansion of the overhead occurs instantaneously. when the signal amplitude decreases, the overhead returns to its initial value with a time constant of approximately one second (see figure 11). during operation the influence of the adap- tive overhead function will not effect the slic performance in the constant current region of operation (see figure 11). if, however, the slic is in the off-hook, constant voltage region of operation then the influence of the adaptive headroom will be apparent as a slight decrease in line voltage (and hence line current) as the slic adjusts to accommodate the larger (voice + metering) signal. line feed if v tr < | vbat2 | -5.7 approx (see formula c in figure 16). the pbl 386 14/1 slic will emulate constant current feed. (references a-c in figure 16). the constant current region is adjustable between 18 ma and 30 ma. if v tr > | vbat2 | -5.7 approx (see formula c in figure 16). the pbl 38615/1 slic will emulate a constant voltage feed with 2 x 25 w source impedance (refer- ences c-e in figure 16). this section is made as steep as possible to switch battery faster. if the loop current is less than 5.5ma then the slic will automatically switch to supply the dc feed via vbat rather than vbat2 (references e in figure 16). this will not give any disturbances on the line. the open loop voltage, v trmax , measured between the tipx and ringx terminals tracks the battery voltage vbat(references j in figure 16). according to the formula: v trmax = | vbat | -4.6 when the line current is approaching open loop conditions (references g in figure 16) the overhead voltage is reduced. the line voltage is kept nearly constant with a steep slope corresponding to 2x25 w (references h in figure 16), to ensure maximum open loop voltage, even with a leaking telephone line. constant current region the constant current (reference a-c in figure 16) is adjusted by connecting a resistor, r lc , between terminal plc and ground according to the equation: r lc = 500 - 10.4 ? in (i lprog ? 32) i lprog i lprog can simplifies to: r lc = 500 i lprog
pbl 386 14/1 13 figure 12. chart describing current in vbat and vbat2. figure 13. chart describing power dissipation with different vbat2. 0 5 10 15 20 25 30 i b2 i b 10000 7500 5000 2500 1000 0 ma 0 100 200 300 400 500 600 700 800 28 v 25 v 22 v 10000 7500 5000 2500 1000 0 v bat 2 mw battery switch to reduce short loop power dissipation, a second battery voltage, off-hook, must be connected to the device via an external diode at terminal vbat2. the slic auto- matically switches between the two battery supply voltages without need for external control. the silent battery switching to vbat occurs when the line current is below 5.5 ma. this means that the current in the on- hook battery is limited to 6 ma. to calculate the switching voltage use this formula (see formula c in figure 16): v tr =| vb2 | -4.4 - 50 i lprog if metering is used see section metering applications down below. connect the terminal vbat2 to the second power supply via the diode d b2 in figure 14. a diode d bb connected between vb and the vb2 power supply, see figure 14, will make sure that the slic continues to work on the second battery even if the first battery voltage disappears. the current commute between the differ- ent batteries as shown in figure 12, note that some current is sourced from vb (typ. 0.5 ma, internal bias current) when the line current is sourced from vb2. the next chart (figure 13) is showing what power dissipa- tion the slic is using with different batter- ies and variation of the line. metering applications, ttx it is very easy to use pbl 386 14/1 in metering applications; simply connect a suitable resistor (r ttx ) in series with a capacitor (c ttx ) between pin rsn and the metering source. capacitor c ttx decouples all dc-voltages that may be superimposed on the metering signal. the metering signal gain can be calculated from the equation: g 4-2ttx = v tr = v ttx z t . z lttx r ttx z t + g 2-4s . (z lttx + 2r f ) a rsn where: v ttx is the wanted metering voltage between the tip and ring terminals z lttx is the line impedance seen by the 12 or 16 khz metering signal, g 2-4s is the transmit gain through the slic, i e 0.5. it is possible to mix voice voltage and metering voltage up to 2.5 vpeak (1.7 vrms), using aov. use following formula to calculate the switching voltage of the battery switch to get enough signal space. v tr =| vb2 | -3.4 -v voice -v ttx - 50 i lprog where: v voice is the voice voltage, normaly 1 v peak v ttx is the the metering voltage in peak.
pbl 386 14/1 14 analog temperature guard the widely varying environmental conditions in which slics operate may lead to the chip temperature limitations being exceeded. the pbl 386 14/1 slic reduces the dc line current and the longitudinal current limit when the chip temperature reaches approximately 145 c and increases it again automatically when the temperature drops. the detector output, det, is forced to a logic low level when the temperature guard is active. the active state temperature guard is exclusively viewed at detector output see section active temperature guard. loop monitoring functions the loop current, ground key and ring trip detectors report their status through a com- mon output, det. the status of the detec- tor pin, det, is selected via the three bit control interface c1, c2 and c3. please refer to section control inputs for a descrip- tion of the control interface. loop current detector the loop current detector indicates that the telephone is off hook and that dc current is flowing in the loop by putting the output pin det, to a logic low level when selected. the loop current detector thresh- old value, i lth , where the loop current de- tector changes state, is programmable with the r ld resistor. r ld connects between pin pld and ground and is calculated accord- ing to: r ld = 500 i lth ground key detector the ground key detector indicates when the ground key is pressed (active) by put- ting the output pin det to a logic high level when selected. the ground key detector circuit senses the difference between tipx and ringx currents. the detector is trig- gered when the difference exceeds the current threshold. ring trip detector ring trip detection is accomplished by connecting an external network to a com- parator in the slic with inputs dt and dr. the ringing source can be balanced or unbalanced e g superimposed on the bat- tery voltage or ground. the unbalanced ringing source may be applied to either the ring lead or the tip lead with return via the other wire. a ring relay driven by the slic ring relay driver connects the ringing source to tip and ring. the ring trip function is based on a polar- ity change at the comparator input when the line goes off-hook. in the on-hook state no dc current flows through the loop and the voltage at comparator input dt is more positive than the voltage at input dr. when the line goes off-hook, while the ring relay is energized, dc current flows and the com- parator input voltage reverses polarity. figure 14 gives an example of a ring trip detection network. this network is applica- ble, when the ring voltage superimposed on the battery voltage is injected on the ring lead of the two-wire port. the dc voltage across sense resistor r rt is monitored by the ring trip comparator input dt and dr via the filter network r 1 , r 2 , r 3 , r 4 , c 1 and c 2 . dt is more positive than dr, with the line on-hook (no dc current). the det output will report logic level high, i.e. the detector is not tripped. when the line goes off-hook, while ringing, a dc current will flow through the loop including sense resistor r rt and will cause the input dt to become more negative than input dr. this chang- es the output on the det pin to logic level low, i.e. tripped detector condition. the system controller (or line card processor) responds by de-energizing the ring relay via the slic, i.e. ring trip. complete filtering of the 20 hz ac compo- nent at terminals dt and dr is not neces- sary. a toggling det output can be exam- ined by a software routine to determine the duty cycle. off-hook condition is indicated when the det output is at logic level low for more than half the time. detector output (det) the pbl 386 14/1 slic incorporates a detector output driver designed as open collector (npn) with a current sinking capa- bility of min 3 ma, and a 10 k w pull-up resistor. the emitter of the drive transistor is connected to agnd. a led can be connected in series with a resistor ( ? 1 k w ) at the det output to visualize, for example loop status. relay driver the pbl 386 14/1 slic incorporates a ring relay driver designed as open collector (npn) with a current sinking capability of 50 ma.the emitter of the drive transistor is connected to bgnd. the relay driver has an internal zener diode clamp to protect the slic from inductive kick-back voltages. no external clamp is needed. control inputs the pbl 386 14/1 slic has three digital control inputs, c1, c2 and c3. a decoder in the slic interprets the control input condition and sets up the command- ed operating state. c1 to c3 are internal pull-up inputs. open circuit state in the open circuit state the tipx and ringx line drive amplifiers as well as other circuit blocks are powered down. this caus- es the slic to present a high impedance to the line. power dissipation is at a minimum and no detectors are active.
pbl 386 14/1 15 resistors (values according to iec- 63 e96 series): r ld = 49.9 k w 1% 1 / 10 w r lc = 18.7 k w 1% 1 / 10 w r ref = 15 k w 1% 1 / 10 w r t = 105 k w 1% 1 / 10 w r tx = 32.4 k w 1% 1 / 10 w r b = 57.6 k w 1% 1 / 10 w r rx = 105 k w 1% 1 / 10 w r 1 = 604 k w 1% 1 / 10 w r 2 = 604 k w 1% 1 / 10 w r 3 = 249 k w 1% 1 / 10 w r 4 = 280 k w 1% 1 / 10 w r rt = 332 w 5% 2 w r rf = 332 w 5% 2 w r f1 , r f2 = line resistor, 40 w 1% match capacitors: (values according to iec-63 e6 series): c b = 100 nf 100 v 20% c b2 = 150 nf 100 v 20% c vcc = 100 nf 10 v 20% c vee = 100 nf 10 v* 20% c tc = 1.0 nf 100 v 20% c rc = 1.0 nf 100 v 20% c hp = 68 nf 100 v 20% c lp = 470 nf 100 v 20% c gg = 220 nf 100 v 20% c 1 = 330 nf 63 v 10% c 2 = 330 nf 63 v 10% c spr = optional 10 v 20% *100v if vee pin connected to vbat, vbat2 figure 14. single-channel subscriber line interface with pbl 386 14/1 and combination codec/filter diodes: d b = 1n4448 d b2 = 1n4448 d bb = 1n4448 ovp: secondary protection ( e g power innovations tisp pbl2). the ground termin- als of the secondary protection should be connected to the common ground on the printed board assembly with a track as short and wide as possible, preferably a groundplane. c vcc codec/ filter system control interface d b2 c rc c lp c hp tip ring ovp +12 v /+5v c 1 r 4 e rg r rt r t kr vb vb2 vcc vcc c gg c 2 r 3 c tc d b vee vee tipx vbat vbat2 nc c2 c3 vcc pld psg lp dt dr plc nc ref vee rrly vtx nc nc ts hp ringx bgnd agnd rsn det c1 r rx r b r ld r lc r ref r f1 r f2 r 1 r 2 d bb c b2 pbl 386 14/1 vb r tx vbat pbl 386 14/1 16 figure 15. line voltage measurment line voltage measurement the line voltage is presented on the detec- tor output as a pulse train (see figure 15) with a frequency inversely proportional to the voltage according to the equation: freq = 10 6 [hz] |v tr | + 1 the line voltage measurement will be started when entering this state from any other state and the slic will be as in active state except for the detector. the data can be used in variety of ways, for example to set transmission parameters in a program- mable codec, in line testing where short circuits on the line can be detected and to control the metering signal amplitude. overvoltage protection pbl 386 14/1 must be protected against overvoltages on the telephone line. the overvoltages could be caused for instance by lightning, ac power contact and induc- tion. refer to maximum ratings, tipx and ringx terminals, for maximum continu- ous and transient voltages. secondary protection the circuit shown in figure 14 utilizes series resistors together with a programmable overvoltage protector (e g power innova- tions tisp pbl2), serving as a secondary protection. the tisp pbl2 is a dual forward-con- ducting buffered p-gate overvoltage pro- tector. the protector gate references the protection (clamping) voltage to negative supply voltage (i.e. the battery voltage, v b ). as the protection voltage will track the negative supply voltage the overvoltage stress on the slic is minimized. positive overvoltages are clamped to ground by a diode. negative overvoltages are initially clamped close to the slic neg- ative supply rail voltage and the protector will crowbar into a low voltage on-state condition, by firing an internal thyristor. a gate decoupling capacitor, c gg , is need- ed to carry enough charge to supply a high enough current to quickly turn on the thyris- tor in the protector. c gg should be placed close to the overvoltage protection device. without the capacitor even the low induc- tance in the track to the v b supply will limit the current and delay the activation of the thyristor clamp. the fuse resistors r f serve the dual purposes of being non- destructive energy dissipators, when transients are clamped and of being fuses, when the line is exposed to a power cross. if a ptc is chosen for r f , note that it is important to always use the ptcs in series with resistors not sensitive to temperature, as the ptc will act as a capacitance for fast transients and therefore will not protect the tisp. power-up sequence no special power-up sequence is neces- sary except that ground has to be present before all other power supply voltages. the digital inputs c1 to c3 are internal pull-up terminals. printed circuit board layout care in printed circuit board (pcb) layout is essential for proper function; the components connecting to the rsn input should be placed in close proximity to that pin, such that no interference is inject- ed into the rsn pin. ground plane sur- rounding the rsn pin is advisable. analog ground (agnd) should be con- nected to battery ground (bgnd) on the pcb in one point. r lc and r ref should be connected to agnd with short leads. pin lp and pin psg are sensitive to leakage currents. r sg and c lp connections to vbat2 should be short and very close to each other. c b and c b2 must be connected with short wide leads.
pbl 386 14/1 17 figure 16. battery feed characteristics (without the protection resistors on the line). a: i l (@ v tr = 0) = i lconst i lconst (typ) = i lprog = 500 r lc (13) b,c: i l = i lconst , v tr (@c)= v app - r feed . i lprog d: r feed = 2 x 25 w e: i l ? 5.5 ma , v tr = v app - r feed . 5.5 ma f: v app (@i l =0) = v b2 - v f * -3.7 * is the forward voltage of diode d vbat2 . g: i l ? 5 ma h: r feed = 2 x 25 w j: v trmax = |v bat | - 4.6 @ i l = 0 ma d b e g h c a v tr [v] i l [ma] f j
pbl 386 14/1 18 information given in this data sheet is believed to be accurate and reliable. however no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of ericsson microelectronics ab. these products are sold only according to ericsson microelectronics general conditions of sale, unless otherwise confirmed in writing. specifications subject to change without notice. 1522-pbl 386 14/1 uen rev. r1a ? ericsson microelectronics ab, 2000 this product is an original ericsson product protected by us, european and other patents. ericsson microelectronics se-164 81 kista-stockholm, sweden telephone: +46 8 757 50 00 ordering information package temp. range part no. 28pin ssop tape & reel 0 - + 70 c pbl 386 14/1 sht

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